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cmos 4-/8-channel analog multiplexers adg508a/adg509a rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2009 analog devices, inc. all rights reserved. features 44 v supply maximum rating v ss to v dd analog signal range single-/dual-supply specifications wide supply range: 10.8 v to 16.5 v extended plastic temperature range: ?40c to +85c low power dissipation: 28 mw maximum low leakage: 20 pa typical available in 16-lead dip/soic and 20-lead plcc/lcc packages superior alternative to dg508a, hi-508 dg509a, hi-509 functional block diagrams adg508a s1 s8 d a0 a1 a2 en decoder 00051-001 figure 1. adg508a adg509a s 1a s 4a da a0 a1 en decoder db s 1b s 4b 00051-002 figure 2. adg509a general description the adg508a and adg509a are cmos monolithic analog multiplexers with eight channels and dual four channels, respec- tively. the adg508a switches one of eight inputs to a common output, depending on the state of three binary addresses and an enable input. the adg509a switches one of four differential inputs to a common differential output, depending on the state of two binary addresses and an enable input. both devices have ttl and 5 v cmos logic-compatible digital inputs. the adg508a and adg509a are designed on an enhanced lc 2 mos process that gives an increased signal capability of v ss to v dd and enables operation over a wide range of supply voltages. the devices can comfortably operate anywhere in the 10.8 v to 16.5 v single- or dual-supply range. these multiplexers also feature high switching speeds and low r on . product highlights 1. single-/dual-supply specifications with a wide tolerance. the devices are specified in the 10.8 v to 16.5 v range for both single and dual supplies. 2. extended signal range. the enhanced lc 2 mos processing results in a high breakdown and an increased analog signal range of v ss to v dd . 3. break-before-make switching. switches are guaranteed break-before-make so that input signals are protected against momentary shorting. 4. low leakage. leakage currents in the range of 20 pa make these multiplexers suitable for high precision circuits.
adg508a/adg509a rev. d | page 2 of 16 table of contents features .............................................................................................. 1 ? functional block diagrams ............................................................. 1 ? general description ......................................................................... 1 ? product highlights ........................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? dual supply ................................................................................... 3 ? single supply ................................................................................. 5 ? absolute maximum ratings ............................................................7 ? esd caution...................................................................................7 ? pin configurations and function descriptions ............................8 ? typical performance characteristics ........................................... 10 ? test circuits ..................................................................................... 11 ? single-supply octal dac application ........................................ 13 ? outline dimensions ....................................................................... 14 ? ordering guide .......................................................................... 16 ? revision history 7 /09rev. c to rev. d changes to table 4 ............................................................................ 8 3/07rev. b to rev. c updated format .................................................................. universal changes to table 3 ............................................................................ 6 inserted table 4 ................................................................................. 7 inserted table 6 ................................................................................. 8 changes to figure 24 ...................................................................... 12 updated outline dimensions ....................................................... 13 changes to ordering guide .......................................................... 15
adg508a/adg509a rev. d | page 3 of 16 specifications dual supply v dd = 10.8 v to 16.5 v, v ss = ?10.8 v to ?16.5 v, unless otherwise noted. table 1. adg508a/ adg509a k version adg508a/ adg509a b version adg508a/ adg509a t version parameter +25c ?40c to +85 +25c ?40c to +85c +25c ?55c to +125c unit comments analog switch analog signal range v ss v ss v ss v ss v ss v ss v min v dd v dd v dd v dd v dd v dd v max r on 280 280 280 typ ?10 v v s +10 v, i ds = 1 ma; see figure 14 450 600 450 600 450 600 max 300 400 300 400 max v dd = 15 v (10%), v ss = ?15 v (10%) 300 400 max v dd = 15 v (5%), v ss = ?15 v (5%) r on drift 0.6 0.6 0.6 %/c typ v s = 0, i ds = 1 ma r on match 5 5 5 % typ ?10 v v s +10 v, i ds = 1 ma i s (off ), off input leakage 0.02 0.02 0.02 na typ v1 = 10 v, v2 = 10 v; see m figure 15 1 50 1 50 1 50 na max i d (off), off output leakage 0.04 0.04 0.04 na typ v1 = 10 v, v2 = 10 v; see m figure 16 adg508a 1 100 1 100 1 100 na max adg509a 1 50 1 50 1 50 na max i d (on), on channel leakage 0.04 0.04 0.04 na typ v1 = v2 = 10 v; see figure 17 adg508a 1 100 1 100 1 100 na max adg509a 1 50 1 50 1 50 na max i diff , differential off output leakage (adg509a only) 25 25 25 na max v1 = 10 v, v2 = 10 v; see m figure 18 digital control v inh , input high voltage 2.4 2.4 2.4 v min v inl , input low voltage 0.8 0.8 0.8 v max i inl or i inh 1 1 1 a max v in = 0 to v dd c in digital input capacitance 8 8 8 pf max dynamic characteristics t transition 1 200 200 200 ns typ v1 = 10 v, v2 = 10 v; see m figure 19 300 400 300 400 300 400 ns max t open 1 50 50 50 ns typ see figure 20 25 10 25 10 25 10 ns min t on (en) 1 200 200 200 ns typ see figure 21 300 400 300 400 300 400 ns max t off (en) 1 200 200 200 ns typ see figure 21 300 400 300 400 300 400 ns max offf isolation 68 68 68 db typ v en = 0.8 v, r l = 1 k, c l = 15 pf, v s = 7 v rms, f = 100 khz 50 50 50 db min
adg508a/adg509a rev. d | page 4 of 16 adg508a/ adg509a k version adg508a/ adg509a b version adg508a/ adg509a t version parameter +25c ?40c to +85 +25c ?40c to +85c +25c ?55c to +125c unit comments c s (off ) 5 5 5 pf typ v en = 0.8 v c d (off) adg508a 22 22 22 pf typ v en = 0.8 v adg509a 11 11 11 pf typ q inj , charge injection 4 4 4 pc typ r s = 0 , v s = 0; see figure 22 power supply i dd 0.6 0.6 0.6 ma typ v in = v inl or v inh 1.5 1.5 1.5 ma max i ss 20 20 20 a typ v in = v inl or v inh 0.2 0.2 0.2 ma max power dissipation 10 10 10 mw typ 28 28 28 mw max 1 sample tested at 25c to ensure compliance.
adg508a/adg509a rev. d | page 5 of 16 single supply v dd = 10.8 v to 16.5 v, v ss = gnd = 0 v, unless otherwise noted. table 2. adg508a/ adg509a k version adg508a/ adg509a b version adg508a/ adg509a t version parameter +25c ?40c to +85c +25c ?40c to +85c +25c ?55c to +125c unit comments analog switch analog signal range gnd gnd gnd gnd gnd gnd v min v dd v dd v dd v dd v dd v dd v max r on 500 500 500 typ gnd v s 10 v, i ds = 0.5 ma; see figure 14 700 1000 700 1000 700 1000 max r on drift 0.6 0.6 0.6 %/c typ v s = 0, i ds = 0.5 ma r on match 5 5 5 % typ gnd v s 10 v, i ds = 0.5 ma i s (off ), off input leakage 0.02 0.02 0.02 na typ v1 = 10 v/gnd, v2 = gnd/10 v; see figure 15 1 50 1 50 1 50 na max i d (off), off output leakage 0.04 0.04 0.04 na typ v1 = 10 v/gnd, v2 = gnd/10 v; see figure 16 adg508a 1 100 1 100 1 100 na max adg509a 1 50 1 50 1 50 na max i d (on), on channel leakage 0.04 0.04 0.04 na typ v1 = v2 = 10 v/gnd; see figure 17 adg508a 1 100 1 100 1 100 na max adg509a 1 50 1 50 1 50 na max i diff , differential off output leakage (adg509a only) 25 25 25 na max v1 = 10 v/gnd, v2 = gnd/10 v; see figure 18 digital control v inh , input high voltage 2.4 2.4 2.4 v min v inl , input low voltage 0.8 0.8 0.8 v max i inl or i inh 1 1 1 a max v in = 0 to v dd c in digital input capacitance 8 8 8 pf max dynamic characteristics t transition 1 300 300 300 ns typ v1 = 10 v/gnd, v2 = gnd/10 v; see figure 19 450 600 450 600 450 600 ns max t open 1 50 50 50 ns typ see figure 20 25 10 25 10 25 10 ns min t on (en) 1 250 250 250 ns typ see figure 21 450 600 450 600 450 600 ns max t off (en) 1 250 250 250 ns typ see figure 21 450 600 450 600 450 600 ns max off isolation 68 68 68 db typ v en = 0.8 v, r l = 1k, c l = 15 pf, v s = 3.5 v rms, f = 100 khz 50 50 50 db min c s (off ) 5 5 5 pf typ v en = 0.8 v c d (off) adg508a 22 22 22 pf typ v en = 0.8 v adg509a 11 11 11 pf typ q inj , charge injection 4 4 4 pc typ r s = 0 , v s = 0 v; see figure 22
adg508a/adg509a rev. d | page 6 of 16 adg508a/ adg509a k version adg508a/ adg509a b version adg508a/ adg509a t version parameter +25c ?40c to +85c +25c ?40c to +85c +25c ?55c to +125c unit comments power supply i dd 0.6 0.6 0.6 ma typ v in = v inl or v inh 1.5 1.5 1.5 ma max power dissipation 10 10 10 mw typ 25 25 25 mw max 1 sample tested at 25c to ensure compliance.
adg508a/adg509a rev. d | page 7 of 16 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter ratings v dd to v ss 44 v v dd to gnd 32 v v ss to gnd C32 v analog inputs 1 voltage at s, d v ss ? 2 v to v dd + 2 v or 20 ma, whichever occurs first continuous current, s or d 20 ma pulsed current s or d 1 ms duration, 10% duty cycle 40 ma digital inputs 1 voltage at a, en v ss ? 4 v to v dd + 4 v or 20 ma, whichever occurs first power dissipation (any package) up to 75c 470 mw derates above 75c by 6 mw/c operating temperature commercial (k version) ?40c to +85c industrial (b version) ?40c to +85c extended (t version) ?55c to +125c storage temperature range ?65c to +150c 1 overvoltage at a, en, s, or d is clamped by diodes. current should be limited to the maximum rating shown in table 3. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
adg508a/adg509a rev. d | page 8 of 16 pin configurations and function descriptions a0 1 en 2 v ss 3 s1 4 a1 16 a2 15 gnd 14 v dd 13 s2 5 s3 6 s4 7 s5 12 s6 11 s7 10 d 8 s8 9 adg508a top view (not to scale) 00051-003 figure 3. adg508a dip, soic 4 v ss 5 s1 6 nc 7 s2 8 s3 18 gnd 17 v dd 16 nc 15 s5 14 s6 19 a2 20 a1 1 nc 2 a0 3 en 13 s7 12 s8 11 nc 10 d 9 s4 adg508a top view (not to scale) nc = no connect 00051-004 figure 4. adg508a lcc 12019 23 4 5 6 7 8 18 17 16 15 14 9 10 11 12 13 nc = no connect v ss s1 nc s2 s3 gnd v dd nc s5 s6 en a0 nc a1 a2 s4 d nc s8 s7 pin 1 identifier adg508a top view (not to scale) 0 0051-005 figure 5. adg508a plcc table 4. adg508a pin function description pin number dip/soic plcc/lcc mnemonic description 1 2 a0 logic control input. 2 3 en active high digital input. when low, the device is disabled and all switches are off. when high, ax logic inputs determine on switches. 3 4 v ss most negative power supply potential in dual supplies. in single-supply applications, it can be connected to ground. 4 5 s1 source terminal 1. can be an input or an output. 5 7 s2 source terminal 2. can be an input or an output. 6 8 s3 source terminal 3. can be an input or an output. 7 9 s4 source terminal 4. can be an input or an output. 8 10 d drain terminal. can be an input or an output. 9 12 s8 source terminal 8. can be an input or an output. 10 13 s7 source terminal 7. can be an input or an output. 11 14 s6 source terminal 6. can be an input or an output. 12 15 s5 source terminal 5. can be an input or an output. 13 17 v dd most positive power supply potential. 14 18 gnd ground (0 v) reference. 15 19 a2 logic control input. 16 20 a1 logic control input. n/a 1 nc no connect. n/a 6 nc no connect. n/a 11 nc no connect. n/a 16 nc no connect. table 5. adg508a truth table a2 a1 a0 en on switch x 1 x 1 x x 1 0 none 0 0 0 1 1 0 0 1 1 2 0 1 0 1 3 0 1 1 1 4 1 0 0 1 5 1 0 1 1 6 1 1 0 1 7 1 1 1 1 8 1 x = dont care.
adg508a/adg509a rev. d | page 9 of 16 a0 1 en 2 v ss 3 s1a 4 a1 16 gnd 15 v dd 14 s1b 13 s2a 5 s3a 6 s4a 7 s2b 12 s3b 11 s4b 10 da 8 db 9 adg509a top view (not to scale) 00051-006 figure 6. adg509a dip, soic 12019 23 4 5 6 7 8 18 17 16 15 14 9 10 11 12 13 nc = no connect v ss s1 a nc s2 a s3 a v dd s1b nc s2b s3b en a0 nc a1 gnd s4a da nc db s4b pin 1 identifier adg509a top view (not to scale) 00051-008 figure 7. adg509a plcc table 6. adg509a pin function description pin number dip/soic plcc/lcc mnemonic description 1 2 a0 logic control input. 2 3 en active high digital input. when low, the device is disabled and all switches are off. when high, ax logic inputs determine on switches. 3 4 v ss most negative power supply potential in dual supplies. in single-supply applications, it can be connected to ground. 4 5 s1a source terminal 1a. ca n be an input or an output. 5 7 s2a source terminal 2a. ca n be an input or an output. 6 8 s3a source terminal 3a. ca n be an input or an output. 7 9 s4a source terminal 4a. ca n be an input or an output. 8 10 da drain terminal a. can be an input or an output. 9 12 db drain terminal b. can be an input or an output. 10 13 s4b source terminal 4b. can be an input or an output. 11 14 s3b source terminal 3b. can be an input or an output. 12 15 s2b source terminal 2b. can be an input or an output. 13 17 s1b source terminal 1b. can be an input or an output. 14 18 v dd most positive power supply potential. 15 19 gnd ground (0 v) reference. 16 20 a1 logic control input. n/a 1 nc no connect. n/a 6 nc no connect. n/a 11 nc no connect. n/a 16 nc no connect. table 7. adg509a truth table a1 a0 en on switch pair x 1 x x 1 0 none 0 0 1 1 0 1 1 2 1 0 1 3 1 1 1 4 1 x = dont care.
adg508a/adg509a rev. d | page 10 of 16 typical performance characteristics the multiplexers are guaranteed functional with reduced single or dual supplies down to 4.5 v. 600 500 400 300 200 100 ?15 ?10 ?5 0 5 10 15 700 0 ?20 20 v d [v s ](v) r on ( ? ) v dd =+5v v ss = ?5v v dd = +10.8v v ss = ?10.8v v dd = +15v v ss = ?15v 00051-009 figure 8. r on as a function of v d (v s ): dual-supply voltage, t a = 25c 10 1 0.1 25 35 45 55 65 85 95 105 115 100 75 125 temperature (c) leakage current (na) v dd = +16.5v v ss = ?16.5v i d (on) i d (off) i s (off) 00051-010 figure 9. leakage current as a function of temperature (note: leakage currents reduce as the supply voltages reduce) 700 600 500 400 300 200 67891011121314 800 100 51 5 supply voltage (v) t transition (ns) single supply dual supply 00051-011 figure 10. t transition vs. supply voltage: dual and single supplies, t a = 25c (note: for v dd and lv ss l < 10 v; v1 = v dd /v ss , v2 = v ss /v dd . (see figure 19 )) 600 500 400 300 200 100 ?15 ?10 ?5 0 5 10 15 700 0 ?20 20 v d [v s ](v) r on ( ? ) v dd =10.8v v ss =0v v dd =15v v ss =0v 00051-012 figure 11. r on as a function of v d (v s ) single-supply voltage, t a = 25c 1.8 1.7 1.6 1.9 1.5 67891011121314 5 supply voltage (v) trigger level (v) 00051-013 1 5 figure 12. trigger levels vs. power supply voltage, dual or single supply, t a = 25c 0.8 0.6 0.4 0.2 678910111213141516 1.0 0 5 supply voltage (v) i dd (ma) 00051-014 1 7 figure 13. i dd vs. supply voltage: dual or single supply, t a = 25c
adg508a/adg509a rev. d | page 11 of 16 test circuits note: all digital input signal rise and fall times measured from 10% to 90% of 3 v. t r = t f = 20 ns. r on =v1/i ds v s sd v1 i ds 00051-015 figure 14. r on d a en gnd 0.8v i s (off) v1 v2 v dd v ss v dd v ss 00051-016 figure 15. i s (off) i d (off) d a en gnd 0.8v v1 v2 v ss v dd v ss v dd 0 0051-017 figure 16. i d (off) d a en gnd 2.4v i d (on) v2 v 1 v dd v ss v dd v ss 00051-018 figure 17. i d (on) da en gnd 0.8v db v1 v2 v ss v dd v ss v dd a a adg509a 00051-019 figure 18. i diff = i db (off) 90% 0v 3v 90% 50% output address drive (v in ) t transition t transition output adg508a 1 a2 a1 a0 50? 1m ? gnd s1 s2?s7 s8 d 35pf v in 2.4v en v dd v ss v dd v ss v1 v2 1 similar connection for adg509a. 00051-020 figure 19. switching time of multiplexer, t transition
adg508a/adg509a rev. d | page 12 of 16 0 v 3 v 50% output address drive (v in ) t open output adg508a 1 a2 a1 a0 50? 1k? gnd s1 s2?s7 s8 d 35pf v in 2.4v en v dd v ss v dd v ss 5v 1 similar connection for adg509a. 00051-021 figure 20. break-before-make delay, t open enable drive (v in ) output 10% 3v 0v 50% 90% t on (en) t off (en) output adg508a 1 a2 a1 a0 50 ? 1k? gnd s1 s2?s8 d 35pf v in en v dd v ss v dd v ss 5v 1 similar connection for adg509a. 00051-022 figure 21. enable delay, t on (en), t off (en) 3v 0v v in v o q inj =cl v o v o d s1 en gnd cl 1nf v o r s v s v dd v ss v dd v ss a0 a1 a2 adg508a 1 1 similar connection for adg509a. 50? v in 0 0051-023 figure 22. charge injection
adg508a/adg509a rev. d | page 13 of 16 single-supply octal dac application the entire system operates from a single 15 v power supply. the adg508a is ideally suited for the application because it has both low charge injection and i s (off) leakage current. the following circuit shows the adg508a connected as a demulti- plexer to provide eight separate, digitally programmable voltages (0 v to 10 v) from the ad7245a . the ad7245a is a complete 12-bit, voltage output dac with output amplifier and zener voltage reference on a monolithic cmos chip. db11 db0 r fb v dd v out r ofs ad7245a v ss dgnd agnd cs wr ldac clr ref out adg508a en d gnd v ss s8 s1 v dd a0 a1 a2 + 1/4 tlc274 v out1 15v 15 v 15 v 0.01f 1/4 tlc274 v out8 15v 0.01f 10f 0.1f 10? 00051-024 figure 23. adg508a in a single-supply octal dac circuit
adg508a/adg509a rev. d | page 14 of 16 outline dimensions controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. corner leads may be configured as whole or half leads. compliant to jedec standards ms-001-ab 073106-b 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 16 1 8 9 0.100 (2.54) bsc 0.800 (20.32) 0.790 (20.07) 0.780 (19.81) 0.210 (5.33) max seating plane 0.015 (0.38) min 0.005 (0.13) min 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.060 (1.52) max 0.430 (10.92) max 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.015 (0.38) gauge plane 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) figure 24. 16-lead plastic dual in-line package [pdip] narrow body (n-16) dimensions shown in inches and (millimeters) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 0.840 (21.34) max 15 0 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) 0 .200 (5.08) max 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.310 (7.87) 0.220 (5.59) 0.005 (0.13) min 0.098 (2.49) max 0.100 (2.54) bsc pin 1 1 8 9 16 seating plane 0.150 (3.81) min 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) figure 25. 16-lead ceramic dual in-line package [cerdip] (q-16) dimensions shown in inches and (millimeters)
adg508a/adg509a rev. d | page 15 of 16 controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-ac 10.00 (0.3937) 9.80 (0.3858) 16 9 8 1 6.20 (0.2441) 5.80 (0.2283) 4.00 (0.1575) 3.80 (0.1496) 1.27 (0.0500) bsc seating plane 0.25 (0.0098) 0.10 (0.0039) 0.51 (0.0201) 0.31 (0.0122) 1.75 (0.0689) 1.35 (0.0531) 0.50 (0.0197) 0.25 (0.0098) 1.27 (0.0500) 0.40 (0.0157) 0.25 (0.0098) 0.17 (0.0067) coplanarity 0.10 8 0 060606-a 45 figure 26. 16-lead standard small outline package [soic_n] narrow body (r-16) dimensions shown in millimeters and (inches) compliant to jedec standards mo-047-aa controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 0.020 (0.50) r bottom view (pins up) 0.021 (0.53) 0.013 (0.33) 0.330 (8.38) 0.290 (7.37) 0.032 (0.81) 0.026 (0.66) 0.056 (1.42) 0.042 (1.07) 0.20 (0.51) min 0.120 (3.04) 0.090 (2.29) 3 4 19 18 8 9 14 13 top view (pins down) 0.395 (10.03) 0.385 (9.78) sq 0.356 (9.04) 0.350 (8.89) sq 0.048 (1.22 ) 0.042 (1.07) 0.048 (1.22) 0.042 (1.07) 0.020 (0.51) r 0.050 (1.27) bsc 0.180 (4.57) 0.165 (4.19) 0.045 (1.14) 0.025 (0.64) r pin 1 identifier figure 27. 20-lead plastic leaded chip carrier [plcc] (p-20) dimensions shown in inches and (millimeters) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 1 20 4 9 8 13 19 14 3 18 bottom view 0.028 (0.71) 0.022 (0.56) 45 typ 0.015 (0.38) min 0.055 (1.40) 0.045 (1.14) 0.050 (1.27) bsc 0.075 (1.91) ref 0.011 (0.28) 0.007 (0.18) r typ 0.095 (2.41) 0.075 (1.90) 0.100 (2.54) ref 0.200 (5.08) ref 0.150 (3.81) bsc 0.075 (1.91) ref 0.358 (9.09) 0.342 (8.69) sq 0.358 (9.09) max sq 0.100 (2.54) 0.064 (1.63) 0.088 (2.24) 0.054 (1.37) 022106-a figure 28. 20-terminal cerami c leadless chip carrier [lcc] (e-20-1) dimensions shown in inches and (millimeters)
adg508a/adg509a rev. d | page 16 of 16 ordering guide model temperature range packag e description package option adg508akn ?40c to +85c 16-lead plas tic dual in-line package [pdip] n-16 adg508aknz 1 ?40c to +85c 16-lead plastic dual in-line package [pdip] n-16 adg508akr ?40c to +85c 16-lead stan dard small outline package [soic_n] r-16 adg508akr-reel ?40c to +85c 16-lead stan dard small outline package [soic_n] r-16 adg508akr-reel7 ?40c to +85c 16-lead st andard small outline package [soic_n] r-16 adg508akrz 1 ?40c to +85c 16-lead standard small outline package [soic_n] r-16 adg508akrz-reel 1 ?40c to +85c 16-lead standard small outline package [soic_n] r-16 adg508akrz-reel7 1 ?40c to +85c 16-lead standard small outline package [soic_n] r-16 adg508akp ?40c to +85c 20-lead plastic leaded chip carrier [plcc] p-20 adg508akp-reel ?40c to +85c 20-lead plastic leaded chip carrier [plcc] p-20 adg508akpz 1 ?40c to +85c 20-lead plastic leaded chip carrier [plcc] p-20 adg508akpz-reel 1 ?40c to +85c 20-lead plastic leaded chip carrier [plcc] p-20 adg508abq ?40c to +85c 16-lead ceramic dual in-line package [cerdip] q-16 adg508atq ?55c to +125c 16-lead ceramic dual in-line package [cerdip] q-16 adg508ate ?55c to +125c 20-terminal ce ramic leadless chip carrier [lcc] e-20-1 ADG508ABCHIPS die adg508atchips die adg509akn ?40c to +85c 16-lead plas tic dual in-line package [pdip] n-16 adg509aknz 1 ?40c to +85c 16-lead plastic dual in-line package [pdip] n-16 adg509akr ?40c to +85c 16-lead stan dard small outline package [soic_n] r-16 adg509akr-reel ?40c to +85c 16-lead stan dard small outline package [soic_n] r-16 adg509akr-reel7 ?40c to +85c 16-lead st andard small outline package [soic_n] r-16 adg509akrz-reel 1 ?40c to +85c 16-lead standard small outline package [soic_n] r-16 adg509akrz-reel7 1 ?40c to +85c 16-lead standard small outline package [soic_n] r-16 adg509akp ?40c to +85c 20-lead plastic leaded chip carrier [plcc] p-20 adg509akp-reel ?40c to +85c 20-lead plastic leaded chip carrier [plcc] p-20 adg509akpz 1 ?40c to +85c 20-lead plastic leaded chip carrier [plcc] p-20 adg509akpz-reel 1 ?40c to +85c 20-lead plastic leaded chip carrier [plcc] p-20 adg509abq ?40c to +85c 16-lead ceramic dual in-line package [cerdip] q-16 adg509atq ?55c to +125c 16-lead ceramic dual in-line package [cerdip] q-16 adg509atq/883b ?55c to +125c 16-lead ceramic dual in-line package [cerdip] q-16 adg509abchips die adg509atchips die 1 z = rohs compliant part. ?2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d00051-0-7 /09(d)

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